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| NJU8752 PRELIMINARY Analog Signal Input Class D Amplifier for Piezo Speaker GENERAL DESCRIPTION NJU8752 is a monaural analog signal input class D amplifier for Piezo speaker. The NJU8752 includes Inversion operational amplifier input circuit, PWM modulator, Output short protector and a low voltage detector. Input part operates on 3.3V(TYP) as power supply and Output part operates up to 13.75V(MAX). Therefore, it drives Piezo speaker with Higher volume and High efficiency. By using equivalent capacitance of Piezo speaker, the NJU8752 is configured as a BTL amplifier capable of operating Piezo speaker with the minimum external components. A BTL configuration eliminates the need for external AC coupling capacitors. Class D achieves high output-efficiency, which leads to low power operation for Piezo speaker, thus the NJU8752 is ideally suited for battery powered applications. PACKAGE OUTLINE NJU8752V FEATURES Piezo Speaker Driving Analog Audio Signal Input, 1-channel BTL Output Standby(Hi-Z), Mute Control Built-in Low Voltage Detector Built-in Short Protector Operating Voltage 3.0 ~ 3.6V(Input) 9.0 ~ 13.75V(Output) C-MOS Technology Package Outline SSOP14 PIN CONFIGURATION VDD IN TEST 1 MUTE VSS OUTP VDDO 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VSS COM TEST 2 STBY VSS OUTN VDDO BLOCK DIAGRAM VDD VSS VDDO IN + COM + Pulse Width Modulator OUTP VSS VDDO OUTN VSS Short Protector Soft Start Control Logic Low Voltage Detector MUTE TEST 1 STBY TEST 2 -1- NJU8752 PIN DESCRIPTION No. 1 2 Function Power Supply: VDD=3.3V Signal Input Maker test 1 3 TEST 1 I This pin must be connected to GND. Mute Control 4 MUTE I Low : Mute ON High : Mute OFF 5 VSS - Positive Power GND : VSS=0V 6 OUTP O Positive Output 7 VDDO - Positive Output Power Supply : VDDO=5.0V~13.75V 8 VDDO - Negative Output Power Supply : VDDO=5.0V~13.75V 9 OUTN O Negative Output 10 VSS - Negative Power GND : VSS=0V Standby Control 11 STBY I Low : Standby ON High : Standby OFF Maker test 2 12 TEST 2 I This pin must be connected to GND. 13 COM I Analog common 14 VSS - Power GND : VSS=0V *Pin No. 5(VSS),10(VSS) and 14(VSS) must be used at the same voltage level *Pin No. 7(VDDO) and 8(VDDO) must be used at the same voltage level. SYMBOL VDD IN I/O - I INPUT PINS STRUCTURE(MUTE, STBY, TEST1, TEST2) VDD Input Terminal VSS Inside Circuit -2- NJU8752 NJU3555 FUNCTIONAL DESCRIPTION (1) Output Signal The OUTP and OUTN generate respectively L-channel and R-channel PWM output signals, which will be converted to analog signal via external 2nd-order or higher LC filter. A switching regulator with a high response against a voltage fluctuation is the best selection for the VDDP and VDDN, which are the power supply for output drivers. To obtain better T.H.D. performance, the stabilization of the power is key. (2) Standby By setting the STBY pin to "L", the standby mode is enabled. In the standby mode, the entire functions of the NJU8752 enter a low-power state, and the output pins(OUTP and OUTN) are in high impedance. (3) Mute By setting the MUTE pin to "L", the Mute function is enabled, and output pins(OUTP and OUTN) output square wave(Duty: 50%). (4) Low Voltage Detector When the power supply voltage drops down to below VDD(MIN), the internal oscillation is halted not to generate unwanted frequency, and the output pins(OUTP and OUTN) become in high impedance. (5) Short Protection Circuit The short protector, which protects the NJU8752 from high short-circuit current, turns off the output driver. After about 5 seconds from the protection, the NJU8752 returns to normal operation. The short protector is enabled in response to the following accidents. -Short between OUTP and OUTN -Short between OUTP and VSS -Short between OUTN and VSS Note 1) The detectable current and the period for the protection depend on the power supply voltage and ambient temperature. Note 2) The short protector is not effective for a long term short-circuit but for an instantaneous accident. Continuous high-current may cause permanent damage to the NJU8752. -3- NJU8752 ABSOLUTE MAXIMUM RATINGS (Ta=25C) PARAMETER Supply Voltage Input Voltage Operating Temperature Storage Temperature Power Dissipation SSOP14 SYMBOL VDD VDDO Vin Topr Tstg PD RATING -0.3 ~ +4.0 -0.3 ~ +15.0 -0.3 ~ VDD+0.3 -40 ~ +85 -40 ~ +125 300 UNIT V V V C C MW Note 1) All voltage are relative to "VSS =0V" reference. Note 2) The LSI must be used inside of the "Absolute maximum ratings". Otherwise, a stress may cause permanent damage to the LSI. Note 3) De-coupling capacitors for VDD(Pin 1)-VSS(Pin 14), VDDO(Pin 7)-VSS(Pin 5) and VDDO(Pin 8)-VSS(Pin 10) should be connected for stable operation. ELECTRICAL CHARACTERISTICS (Ta=25C, VDD=3.3V, VDDO=12.0V, VSS=0V, Input Signal=1kHz, Input Signal Level=200mVrms, Frequency Band=20Hz~20kHz, Load Capacitance=0.8F, 2nd-order 34kHz LC Filter (Q=0.75)) PARAMETER VDD Supply Voltage VDDO Supply Voltage Output Power Efficiency Output T.H.D. Output Power S/N Dynamic Range Maximum Mute Attenuation Operating Current(Stanby) Operating Current (No signal input) Input Voltage Input Leakage Current SYMBOL CONDITIONS MIN 3.0 9.0 80 T.B.D T.B.D -90 0.7VDD 0 TYP 3.3 12.0 T.B.D T.B.D T.B.D MAX 3.6 13.75 0.1 10 10 VDD 0.3VDD 1.0 UNIT V V % % W/ch dB dB dB A mA V V A Note Eeff T.H.D. Po SN Drange MAT IST IDD VIH VIL ILK Output T.H.D.=10% Po= T.B.D Output T.H.D.=10% A weight A weight 4 No-load operating No Signal Input -4- NJU8752 NJU3555 Note 4) Test system of the output T.H.D., S/N, Dynamic Range The output T.H.D., S/N and dynamic range are tested in the system shown in Figure 1, where a 2nd-order LC LPF and another filter incorporated in an audio analyzer are used. Input Signal NJU8752 2nd-order LC LPF Filter 20kHz (AES17) THD Measuring Apparatus NJU8752 Test Board Audio Analyzer Figure 1. Output T.H.D., S/N and Dynamic Range Test System 2nd-order LPF Filters : fc=34kHz / Refer to "Typical Application Circuit". : 22Hz HPF + 20kHz LPF(AES17) (with the A-Weight filter for S/N and Dynamic-range tests) -5- NJU8752 TYPICAL APPLICATION CIRCUIT 10uF 0.1uF VDD VDD(1) VSS(14) IN 10uF IN(2) COM(13) MUTE(4) STBY(11) TEST1(3) TEST2(12) VDDO(8) VSS(10) 10uH OUTP(6) 0.1uF 10uH Piezo Speaker 0.1uF NJU8752 0.47uF OUTN(9) 0.1uF VDDO(7) VSS(5) 0.1uF 10uF VDD 10uF VDD Figure 2. Application Circuit example Note 5) De-coupling capacitors must be connected between each power supply pin and GND. Note 6) A switching regulator with a high response against a voltage fluctuation is ideal for the VDDO to obtain better T.H.D. performance. Note 7) Testing actual samples in your system is highly recommended. The typical application circuit is one of examples. Note 8) The transition time of MUTE and STBY signals must be less than 100us. Otherwise, a malfunction might occur. Note 9) (1)-(14) indicates pin number. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -6- |
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